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Samsung will start 3 volume chip production with high volume next year

Samsung will start 3 volume chip production with high volume next year

Samsung Foundry, the second largest independent foundry in the world after TSMC, has made some changes to its 3nm process node according to AnandTech. The first chips from Samsung Foundry that were produced using the 3nm process, 3GAE (3nm Gate-All-Around Early), will reportedly go through volume production a year later than usual. It was also removed from Samsung’s roadmap, indicating that 3GAE can only be produced for internal use.
A Samsung representative said: “Regarding the 3GAE process, we have been in discussions with customers and expect to mass-produce 3GAE by 2022.” 3GAE’s successor, the 3GAP (3nm Gate-All-Around Plus) node, is still listed on the roadmap with volume production expected to begin in 2023. The aforementioned roadmap was unveiled at the Foundry Forum 2021 in China. Samsung Foundry introduced its updated technical roadmap which was then published on Baidu and Weibo.
As for the chips using the older FinFET transistor architecture, Samsung has added 5LPP and 4LPP to the roadmap with high-volume production kits for 2021 and 2022, respectively. Samsung unveiled its 3GAE and 3GAP nodes in May 2019, announcing that they would deliver a 35% increase in performance, a 50% reduction in power consumption compared to 7LPP which is currently the previous generation process node.

At the same time back in 2019, volume production using 3GAA (Gate-All-Around transistor architecture) was announced to start at the end of 2021. With the new launch date 2022 for the 3nm Gate-All-Around Early process, it can be concluded that there has been a slight delay on Samsung’s part or a miscalculation. In any case, it is not considered a big deal, as Sammy’s early nodes are not used by producers to a great extent.

Just a few days ago, Samsung Foundry dropped a 3nm chip using its Gate-All-Around (GAA) transistor architecture. Taping out a piece is the final act of its design cycle that results in one of two outcomes: chip design works or not. In the case of the latter, a minor solution may be required, or a complete overhaul of the design may be required.

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