Next to the announcement of the new 7nm Qualcomm Snapdragon 8cx processor for the company's line of next generation premium tier All Time Connected PCs, in the demo room today, we saw a wafer with chips built on TSMC's 7nm.
With this image, we can do a primary thing: train the door size. Based on our estimates, we can see about 36 chips from top to bottom, and 22.2 chips from side to side. On a regular 300mm wafer, and give a little to the small amount of unused silicon from dying to die so that they can be cut, we get a reasonable door size of 112 square millimeters. This is what we expect to be the upper limit, and the end result may be lower.
The 112 mm2 is from a height of 8.3 mm and a width of 13.5 mm (which technically gives 1
In the slides
Qualcomm stated that 8cx has double transistors. We assume it's a comparison with Snapdragon 850, which is an overclocked S845, which had 5.3 billion transistors on the 10nm node. This would make 8cx to around ~ 10 billion transistors (to 10.6b) of 112 mm2, or equivalent to 89-95 million transistors per square millimeter (MTr / mm2) . Snapdragon 845/850 at 10nm would have been 56 MTr / mm2.
* It has been noticed that the slide "2x transistors" refers only to the size of the graphics on the chip and not the entire chip itself. The table is updated.
|Nozzle Size and Transistor Counter|
|AnandTech||Process Code|| Nozzle Size
| Door area
||7nm TSMC|| 8.3×13.5 > 5.3b
|Snapdragon 845/850||10LPP Samsung||94||5.3b||56.4|
|Snapdragon 835||10LPE Samsung||72.3||3.0b||41.5|
|Kirin 980||7nm TSMC||74.13||6.9 b||93.1|
|Kirin 970||10nm TSMC||10nm TSMC||10nm TSMC||] 9.75 x 9.92||96.72||5.5 b||56.9|
|Kirin 960||16nm TSMC||10, 77 x 10.93||117.72||4.0 b||34.0|
| Apple A12 Bionic||7nm TSMC||9.89 x 8.42||83.27||6.9 b||82.9|
|Exynos 9810||10LPP Samsung||10.37 x 11.47||118.94||19659008]?|
|8-core Ryzen||14nm GloFo||22.06 x 9.66||192||4.8 b||25.0|
|Skylake 4 + 2 ] 14nm Intel||13.31 x 9.19||122||1.75 b||14.3|
|* You Pper Bound|
More information as we get it.