Home / Technology / AMD triples Zen 3 CPU cache using 3D stacking technology

AMD triples Zen 3 CPU cache using 3D stacking technology



Yesterday at Computex 2021, AMD CEO Lisa Su presented the company’s next big performance game – 3D-stacked chips, so that the company can triple the amount of L3 cache on the flagship Zen 3-CPUs.

The technology is exactly as it sounds – a layer of SRAM cache that sits on top of the Complex Core Die (CCD) on the CPU itself. The current Zen 3 architecture integrates 32MiB L3 cache per eight-core chip – giving a total of 64MiB for a 12- or 16-core chip like the Ryzen 9 5900X or 5950X. The new technology adds an additional 64MiB L3 cache to the top of each chip’s CCD, bound with through-silicon vias (TSVs).

The extra 64MiB L3 cache does not extend the CCD width, resulting in a need for structural silicon to balance the pressure from the CPU cooling system. Computing and cache nozzles are both thinned in the new design, so it can share substrate and heat dissipator technology with today’s Ryzen 5000 processors.

Triple the L3 cache on the Ryzen 5000 provides performance gains under some workloads – especially archive compression / decompression and gaming – like those seen with brand new CPU generations. AMD demonstrated performance boost via a Gears of War 5 demo. Paired with an unspecified GPU and clocked at a fixed speed of 4 GHz, a current model 5900X system achieved 184 frames per second – while the triple buffer prototype managed 206 frames per second, a gain of about 12 percent.

AMD claims an average of 15 percent improved gaming performance with the new technology, ranging from a low level of 4 percent for League of Legends to a high of 25 percent for Monster Hunter: World. This performance improvement requires neither less process node nor increased clock speed – which is particularly interesting, at a time when clock speeds have largely hit a wall, and a physics-specific end to process node shrinkage seems to be on the horizon as well.

Anandtech’s Ian Cutress notes that AMD’s new 3D chiplet stacking process is clearly TSMC’s SoIC Chip-on-Wafer technology in action. While AMD so far limits itself to at least two teams, TSMC has demonstrated as many as 12 teams in action. The problem here is thermal – adding RAM is an almost ideal use of the technology, since extra silicon does not generate much in the way of additional heat. Stacking CPU on CPU would be far more problematic.

AMD states that the redesigned 5900X will go into production later this year – well before Zen 4’s planned launch in 2022. For now, AMD is focusing only on the new technology for “high-end Ryzen” processors – it was not mentioned Epyc, and the extra silicon required for the extra cache makes it a likely nonstarter for budgeters, given the current shortage of materials.

Listing image of AMD


Source link