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Home / Technology / AMD Patent reveals hybrid CPU-FPGA designs that can be activated by Xilinx Tech

AMD Patent reveals hybrid CPU-FPGA designs that can be activated by Xilinx Tech



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Although often not as good as CPUs alone, FPGAs can do a fantastic job of accelerating specific tasks. Although it accelerates to act as a substance for large data center services that increase AI performance, an FPGA in the hands of a skilled engineer can download a wide range of tasks from a CPU and speed processes. Intel has been talking a big game about integrating Xeons with FPGAs for the past six years, but that has not resulted in a single product hitting the line-up. However, a new patent from AMD may mean that the FPGA newcomer may be ready to make one of its own.

In October, AMD announced plans to buy Xilinx as part of a major push into the data center. On Thursday, the US Patent and Trademark Office (USPTO) published an AMD patent for integrating programmable execution devices with a CPU. AMD made 20 claims in the patent application, but the essence is that a processor can include one or more execution units that can be programmed to handle different types of custom instruction sets. That̵

7;s exactly what an FPGA does. It may take some time before we see products based on this design, as it seems a little too early to be a part of CPUs that are included in recent EPYC leaks.

While AMD has made waves with the briquette designs for Zen 2 and Zen 3 processors, that does not seem to be what is happening here. The programmable device in AMD’s FPGA patent actually shares registers with the processor’s floating point and integer execution devices, which would be difficult, or at least very slow, if they are not in the same package. This type of integration should make it easy for developers to merge these custom instructions into applications, and the CPU will only know how to transfer them to the FPGA on the processor. These programmable devices can handle atypical data types, especially FP16 values ​​(or half-precision) that are used to speed up AI training and inference.

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For multiple programmable devices, each device can be programmed with a different set of specialized instructions, allowing the processor to accelerate multiple instruction sets, and these programmable EUs can be reprogrammed on the go. The idea is that when a processor loads a program, it also loads a bit file that configures the programmable drive to increase the speed of certain tasks. The CPU’s own decoding and shipping unit can address the programmable unit and transmit the customized instructions to be processed.

AMD has been working on various ways to speed up AI computing for many years. First, the company announced and released the Radeon Impact series of AI accelerators, which were just large, headless Radeon graphics processors with custom drivers. The company doubled that with the release of MI60, the first 7 nm GPU before the launch of the Radeon RX 5000 series, in 2018. A shift to focus on AI via FPGA after the Xilinx acquisition makes sense, and we’re excited to see what the company invents.


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